1. Field of the Invention
The present invention relates to semiconductor devices and methods for manufacturing the semiconductor devices. The present invention especially relates to a technique for miniaturizing semiconductor integrated circuits.
In this specification, a “semiconductor device” refers to a device which can function by utilizing semiconductor characteristics; a semiconductor element, an electro-optical device, a memory device, a semiconductor circuit, and an electronic apparatus are all included in the category of the semiconductor device.
2. Description of the Related Art
A transistor is widely known as one of semiconductor elements and often used for memory devices such as SRAM and DRAM, and display devices including a liquid crystal element, an EL element, or the like. A reduction in area per transistor is needed for higher integration and higher definition of such semiconductor devices. However, in a transistor with a small area, particularly in a transistor having a channel length of 100 nm or shorter, a punch-through phenomenon in which electrical continuity between a source and a drain is established due to a short-channel effect is likely to occur, so that the transistor becomes incapable of functioning as a switching element, which has been considered as a problem.
Against such a problem, a method for forming a three-dimensional transistor in which the area occupied by one transistor is reduced and the effective channel length is maintained so as not to cause a short-channel effect has been proposed.
For example, Patent Document 1 discloses an inversed staggered transistor in which a channel is formed over a portion between two gate electrodes so that the channel length is increased by steps of the gate electrodes.
Patent Document 2 discloses an inversed staggered transistor having a structure, in addition to the structure disclosed in Patent Document 1, in which the thickness of each gate electrode is set to larger than the width thereof so that a channel length is relatively increased by an increase in thickness of the gate electrodes.
Patent Document 3 discloses an inversed staggered transistor in which a gate electrode with a depressed portion is formed and a channel is formed over the depressed portion so that the channel length is increased by steps of the gate electrode.
Patent Document 4 discloses an inversed staggered transistor having a structure, in addition to the structure disclosed in Patent Document 3, in which the thickness of the gate electrode with a depressed portion is set to larger than the distance between steps of the gate electrode so that a channel length is relatively increased by an increase in thickness of the gate electrode. According to the above, even when the area occupied by one transistor is reduced and the planar size of the transistor is reduced, a channel length which hardly generates a punch-through phenomenon due to a short-channel effect can be obtained.